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1 ISL89163, isl89164, isl89165 high speed, dual channel, 6a, power mosfet driver with enable inputs ISL89163, isl89164, isl89165 the ISL89163, isl89164, and isl89165 are high-speed, 6a, dual channel mosfet drivers with enable inputs. these parts are identical to the isl89160, isl89161, isl89162 drivers but with an added enable input for each channel occupying nc pins 1 and 8 of the isl89160, isl89161, isl89162. precision thresholds on all logic inputs allow the use of external rc circuits to generate accurate and stable time delays on both the main channel inputs, ina and inb, and the enable inputs, ena and enb. the precision delays capable of these precise logic threshold makes these parts very useful for dead time control and synchronous rectifiers. note that the enable and input logic inputs can be interchanged for alternate logic implementations. three input logic thresholds are available: 3.3v (cmos), 5.0v (cmos or ttl compatible), and cmos thresholds that are proportional to vdd. at high switching frequencies, these mosfet drivers use very little internal bias currents. separate, non-overlapping drive circuits are used to drive each cmos output fet to prevent shoot-thru currents in the output stage. the under voltage lockout (uv) insures that driver outputs remain off (low) during turn-on until vdd is sufficiently high for correct logic control. this prevents unexpected glitches when vdd is being turn-on or turn-off. features ? dual output, 6a peak current (sink and source) ? dual and-ed input logic, ( in put and en able) ? typical on-resistance <1 ? specified miller plateau drive currents ? very low thermal impedance ( jc = 3 c/w ) ? input logic levels for 3. 3v cmos, 5v cmos, ttl and logic levels proportional to v dd ? hysteretic logic inputs for high noise immunity ? precision threshold inputs for time delays with external rc components ? ~ 20ns rise and fall time driving a 10nf load. ? low operating bias currents applications ? synchronous rectifier (sr) driver ? switch mode power supplies ? motor drives, class d amplifiers, ups, inverters ? pulse transformer driver ? clock/line driver related literature ? an1602 ?isl8916xa, isl8916xb, isl8916xc, evaluation board user?s guide? ? an1603 ?isl6752_54 evaluation board application note? typical application temp stable logic thresholds 8 6 7 1 4 3 2 5 epad v dd 4.7f enb ena ina inb gnd outa outb 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 option b thresholds (5.0v) temperature (c) negative threshold limits positive threshold limits caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. october 12, 2010 fn7707.0
ISL89163, isl89164, isl89165 2 fn7707.0 october 12, 2010 block diagram outx vdd inx gnd for clarity, only one channel is shown epad for proper thermal and electrical performance, the epad must be connected to the pcb ground plane. separate fet drives, with non- overlapping outputs, prevent shoot-thru currents in the output cmos fets resulting with very low high frequency operating currents. isl89164, isl89165 ISL89163 10k enx enx and inx inputs are identical and may be interchanged for alternate logic for options a and b, the uv comparator holds off the outputs until vdd ~> 3.3vdc. for option c, the uv release is ~> 6.5v pin configurations ISL89163fr, ISL89163fb (8 ld tdfn, epsoic) top view isl89164fr, isl89164fb (8 ld tdfn, epsoic) top view isl89165fr, isl89165fb (8 ld tdfn, epsoic) top view ena ina gnd inb outb vdd outa enb 1 2 3 4 5 6 7 8 ena ina gnd inb /outb vdd /outa enb 1 2 3 4 5 6 7 8 ena ina gnd inb /outb vdd enb /outa 1 2 3 4 5 6 7 8 pin descriptions pin number symbol description (see truth table for logic polarities) 1 ena channel a enable, 0v to vdd 2 ina channel a input, 0v to vdd 3gndpower ground, 0v 4 inb channel b enable, 0v to vdd 5outb, /outb channel b output 6 vdd power input, 4.5v to 16v 7outa, /outa channel a output, 0v to vdd 8 enb channel b enable, 0v to vdd epad power ground, 0v enx* inx* outx* 0 0 0 0 1 0 1 0 1 1 1 0 outx enx inx enx* inx* outx* 0 0 0 0 1 0 1 0 0 1 1 1 outx enx inx *substitute a or b for x non-inverting inverting
ISL89163, isl89164, isl89165 3 fn7707.0 october 12, 2010 ordering information part number (notes 1, 2, 3, 4) part marking temp range (c) input configuration input logic package (pb-free) pkg. dwg. # ISL89163frt a z 163a -40 to +125 non-inverting 3.3v 8 ld 3x3 tdfn l8.3x3i ISL89163frt b z 163b -40 to +125 5.0v 8 ld 3x3 tdfn l8.3x3i ISL89163frt c z 163c -40 to +125 vdd 8 ld 3x3 tdfn l8.3x3i isl89164frt a z 164a -40 to +125 inverting 3.3v 8 ld 3x3 tdfn l8.3x3i isl89164frt b z 164b -40 to +125 5.0v 8 ld 3x3 tdfn l8.3x3i isl89164frt c z 164c -40 to +125 vdd 8 ld 3x3 tdfn l8.3x3i isl89165frt a z 165a -40 to +125 inverting + non- inverting 3.3v 8 ld 3x3 tdfn l8.3x3i isl89165frt b z 165b -40 to +125 5.0v 8 ld 3x3 tdfn l8.3x3i isl89165frt c z 165c -40 to +125 vdd 8 ld 3x3 tdfn l8.3x3i ISL89163fbe a z 89163 fbeaz -40 to +125 non-inverting 3.3v 8 ld epsoic m8.15d ISL89163fbe b z 89163 fbebz -40 to +125 5.0v 8 ld epsoic m8.15d ISL89163fbe c z 89163 fbecz -40 to +125 vdd 8 ld epsoic m8.15d isl89164fbe a z 89164 fbeaz -40 to +125 inverting 3.3v 8 ld epsoic m8.15d isl89164fbe b z 89164 fbebz -40 to +125 5.0v 8 ld epsoic m8.15d isl89164fbe c z 89164 fbecz -40 to +125 vdd 8 ld epsoic m8.15d isl89165fbe a z 89165 fbeaz -40 to +125 inverting + non- inverting 3.3v 8 ld epsoic m8.15d isl89165fbe b z 89165 fbebz -40 to +125 5.0v 8 ld epsoic m8.15d isl89165fbe c z 89165 fbecz -40 to +125 vdd 8 ld epsoic m8.15d notes: 1. add ?-t?, suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). inte rsil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. input logic voltage: a = 3.3v, b = 5.0v, c = vdd. 4. for moisture sensitivity level (msl), please see device in formation page for ISL89163, isl89164, isl89165 . for more information on msl, plea se see technical brief tb363 .
ISL89163, isl89164, isl89165 4 fn7707.0 october 12, 2010 absolute maximum ratings thermal information supply voltage, v dd relative to gnd . . . . . . . . -0.3v to 18v logic inputs (ina, inb, ena, enb) gnd - 0.3v to v dd + 0.3v outputs (outa, outb). . . . . . . . . gnd - 0.3v to v dd + 0.3v average output current (note 7) . . . . . . . . . . . . . . . 150ma esd ratings human body model class 2 (tested per jesd22-a114e) 2000v machine model class b (tested per jesd22-a115-a) . . . 200v charged device model class iv . . . . . . . . . . . . . . . . . 1000v latch-up (tested per jesd-78b; class 2, level a) output current . . . . . . . . . . . . . . . . . . . . . . . . . 500 ma thermal resistance (typical) ja (c/w) jc (c/w) 8 ld tdfn package (notes 5, 6). . . 44 3 8 ld epsoic package (notes 5, 6) . 42 3 max power dissipation at +25c in free air . . . . . . . . . 2.27w max power dissipation at +25c with copper plane . . . 33.3w storage temperature range . . . . . . . . . . . . -65c to +150c operating junction temp range . . . . . . . . . -40c to +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/pb-freereflow.asp maximum recommended operating conditions junction temperature. . . . . . . . . . . . . . . . . -40c to +125c options a and b supply voltage, v dd relative to gnd . . . . . . . . 4.5v to 16v logic inputs (ina, inb, ena, enb) . . . . . . . . . . 0v to vdd outputs (outa, outb) . . . . . . . . . . . . . . . . . . 0v to vdd option c supply voltage, v dd relative to gnd . . . . . . . . 7.5v to 16v logic inputs (ina, inb, ena, enb) . . . . . . . . . . 0v to vdd outputs (outa, outb) . . . . . . . . . . . . . . . . . . 0v to vdd caution: do not operate at or near the maximum rati ngs listed for extended periods of time. exposure to such conditions may adversely im pact product reliability and result in failures not covered by warranty. notes: 5. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379 for details. 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 7. the average output current, when driving a power mosfet or si milar capacitive load, is the average of the rectified output current. the peak output currents of this driv er are self limiting by transconductance or r ds(on) and do not required any external components to minimize the peaks. if the output is driving a non-capacitive load, such as an led, maximum output current must be limited by external means to less than the specified absolute maximum. dc electrical specifications v dd = 12v, gnd = 0v, no load on outa or outb, unless otherwise specified. boldface limits apply over the operating junction temperature range, -40c to +125c. parameters symbol test conditions t j = +25c t j = -40c to +125c units min typ max min (note 8) max (note 8) power supply voltage range (option a and b) v dd --- 4.5 16 v voltage range (option c) v dd --- 7.5 16 v v dd quiescent current i dd enx = inx = gnd - 5 - - - ma ina = inb = 1mhz, square wave - 25 - - ma undervoltage vdd undervoltage lock-out (option a or b) (note 12) v uv ena = enb = true ina = inb = true (note 9) -3.3- - - v vdd undervoltage lock-out (option c) v uv -6.5- - - v hysteresis (option a or b) - ~25 - - - mv hysteresis (option c) - ~0.95 - - - v
ISL89163, isl89164, isl89165 5 fn7707.0 october 12, 2010 inputs input range for ina, inb v in option a, b, or c - - - gnd v dd v logic 0 threshold for ina, inb, ena, enb (note 11) v il option a, nominally 37% x 3.3v - 1.22 - 1.12 1.32 v option b, nominally 37% x 5.0v - 1.85 - 1.70 2.00 v option c, nominally 20% x 12v (note 9) -2.4- 2.00 2.76 v logic 1 threshold for ina, inb, ena, enb (note 11) v ih option a, nominally 63% x 3.3v - 2.08 - 1.98 2.18 v option b, nominally 63% x 5.0v - 3.15 - 3.00 3.30 v option c, nominally 80% x12v (note 9) -9.6- 9.24 9.96 v input capacitance of ina, inb, ena, enb (note 10) c in -2- - - pf input bias current for ina, inb, ena, enb i in gnd ISL89163, isl89164, isl89165 6 fn7707.0 october 12, 2010 ac electrical specifications v dd = 12v, gnd = 0v, no load on outa or outb, unless otherwise specified. boldface limits apply over the operating junction temperature range, -40c to +125c. parameters symbol test conditions /notes t j = +25c t j = -40c to +125c units min typ max min max output rise time (see figure 2) t r c load = 10 nf, 10% to 90% -20- - 40 ns output fall time (see figure 2) t f c load = 10 nf, 90% to 10% -20- - 40 ns output rising edge propagation delay for non-inverting inputs (see figure 1) t rdlyn no load - 25 - - 50 ns output rising edge propagation delay with inverting inputs (see figure 1) t rdlyi no load - 25 - - 50 ns output falling edge propagation delay with non-inverting inputs (see figure 1) t fdlyn no load - 25 - - 50 ns output falling edge propagation delay with inverting inputs (see figure 1) t fdlyi no load - 25 - - 50 ns rising propagation matching (see figure 1) t rm -<1ns- - - ns falling propagation matching (see figure 1) t fm -<1ns- - - ns miller plateau sink current (see test circuit figure 3) -i mp v dd = 10v, v miller = 5v -6- - - a -i mp v dd = 10v, v miller = 3v -4.7- - - a -i mp v dd = 10v, v miller = 2v -3.7- - - a miller plateau source current (see test circuit figure 4) i mp v dd = 10v, v miller = 5v -5.2- - - a i mp v dd = 10v, v miller = 3v -5.8- - - a i mp v dd = 10v, v miller = 2v -6.9- - - a
ISL89163, isl89164, isl89165 7 fn7707.0 october 12, 2010 test waveforms and circuits figure 1. prop delays and matching figure 2. rise/fall times figure 3. miller plateau sink current test circuit figure 4. miller plateau source current test circuit figure 5. miller plateau sink current figure 6. miller plateau source current ina, inb outa outb 0v 3.3v* t rdly t rdly 50% 50% t fdly t fdly * logic levels: a option = 3.3v, b option = 5.0v, c option = vdd t rm t fm /outb /outa outa or outb t r t f 90% 10% v miller 10v +i sense -i sense 10f 0.1f 50m 200ns 10k isl8916x 10nf v miller 10v +i sense -i sense 10f 0.1f 50m 200ns 10k isl8916x 10nf 200ns v miller -i mp v out current through 0.1 resistor 10v 0a 0v 200ns v miller i mp v out current through 0.1 resistor 0
ISL89163, isl89164, isl89165 8 fn7707.0 october 12, 2010 typical performance curves figure 7. i dd vs v dd (static) figure 8. i dd vs v dd (1 mhz) figure 9. i dd vs frequency (+25c) figure 10. r ds(on) vs temperature figure 11. option a thresholds figure 12. option b thresholds 2.0 2.5 3.0 3.5 4 8 12 16 static bias current (ma) v dd +125c +25c -40c +125c +25c -40c 20 25 30 35 15 10 5 4 8 12 16 1mhz bias current (ma) v dd 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.6 2.0 frequency (mhz) i dd (ma) no load 5v 10v 16v 12v 1.8 1.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 -45 -20 5 30 55 80 105 130 r ds(on) ( ) temperature (c) v out low v out high 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -45 -20 5 30 55 80 105 130 input logic thresholds (3.3v) temperature (c) positive threshold negative threshold 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -45 -20 5 30 55 80 105 130 input logic thresholds (3.3v) temperature (c) positive threshold negative threshold 3.5
ISL89163, isl89164, isl89165 9 fn7707.0 october 12, 2010 functional description overview the ISL89163, isl89164, isl89165 mosfet drivers incorporate several features optimized for synchronous rectifier (sr) driver applicat ions including precision input logic thresholds, enable inputs, undervoltage lock-out, and high output drive currents. the precision input thresholds facilitate the use of an external rc network to delay the rising or falling propagation of the driver output. this is a useful feature for adjusting when the srs turn-on relative to the primary side fets. in a similar manner, these drivers can also be used to control the turn-on/off timing of the primary fets. the enable inputs (ena, enb) are used to emulate diode operation of the srs by disab ling the driver output when it is necessary to prevent negative currents in the srs. an example is turning off th e srs when the power supply output is turned off. this prevents the output capacitor from being discharged through the output inductor. if this is allowed to happen, the voltage across the output capacitor will ring negative possibly damaging the capacitor (if it is polarized) and probably damaging the load. another example is preventing circulating currents between paralleled power supplies during no or light load conditions. during light load conditions (expecially when active load sharing is not active), energy will be transfered from the paralled power supply that has a higher voltage to the paralleled power supply with the lower voltage. consequently, th e energy that is absorbed by the low voltage output is then transfered to the primary side causing the bus voltage to increase until the primary side is damaged by excessive voltage. to prevent unexpected glitches on the output of the ISL89163, isl89164, isl89165 during power-on or power-off when v dd is very low, the undervoltage (uv) lock-out prevents the outputs of the ISL89163, isl89164, isl89165 driver from turning on. the a and b input threshold options force the driver outputs to be low when vdd < ~3.2 vdc regardless of the input logic states. the c option shuts down when v dd < ~ 6.5 vdc. application information precision thresholds for time delays three input logic voltage le vels are supported by the ISL89163, isl89164, isl89165. option a is used for 3.3v logic, option b is used for 5.0v logic, and option c is used for higher voltage logic when it is desired to have voltage thresholds that are proportional to v dd . the a and b options have nominal thresholds that are 37% and 63% of 3.3v and 5.0v respectively and the c option is 20% and 80% of vdd. in figure 15, r del and c del delay the rising edge of the input signal. for the falling edge of the input signal, the diode shorts out the resistor resulting in a minimal falling edge delay. the 37% and 63% thresholds of options a and b were chosen to simplify the calculations for the desired time delays. when using an rc circuit to generate a time delay, the delay is simply t (secs) = r (ohms) x c (farads). please note that this equation only applies if the input logic voltage is matched to the 3.3v or 5v threshold options. if the logic high amplitude is not equal to 3.3v or 5v, then the equations in equation 1 can be used for more precise delay calculations. figure 13. output rise/fall time figure 14. propagation delay vs v dd typical performance curves (continued) 15 20 25 -45 -20 5 30 55 80 105 130 rise/fall time (ns) temperature (c) fall time, c load = 10nf rise time, c load = 10nf 15 20 25 30 5 7 9 11 13 15 propagation delay (ns) v dd output falling prop delay output rising prop delay enx inx r del c del d outx figure 15. delay using rcd network
ISL89163, isl89164, isl89165 10 fn7707.0 october 12, 2010 in this example, the high logic voltage is 10v, the positive threshold is 63% of 5v and the low level logic is 0.3v. note the the rising edge propagation delay of the driver must be added to this value. the minimum recommended value of c is 100pf. the parasitic capacitance of the pcb and any attached scope probes will introduce significant delay errors if smaller values are used. larger values of c will further minimize errors. acceptable values of r are primarily effected by the source resistance of the logic inputs. generally, 100 resistors or larger are usable. power dissipation of the driver the power dissipation of the ISL89163, isl89164, isl89165 is dominated by the losses associated with the gate charge of the driven br idge fets and the switching frequency. the internal bias current also contributes to the total dissipation but is usually not significant as compared to the gate charge losses. figure 16 illustrates how the gate charge varies with the gate voltage in a typical power mosfet. in this example, the total gate charge for v gs = 10v is 21.5nc when v ds = 40v. this is the charge that a driver must source to turn-on the mosfet and must sink to turn-off the mosfet. equation 2 shows calculating the power dissipation of the driver: where: freq = switching frequency, v gs = v dd bias of the ISL89163, isl89164, isl89165 q c = gate charge for v gs i dd (freq) = bias current at the switching frequency (see figure 7) r ds(on) = on-resistance of the driver r gate = external gate resistance (if any). note that the gate power dissipation is proportionally shared with the external gate resistor. do not overlook the power dissipated by the external gate resistor. (eq. 1) v h 10v = high level of the logic signal into the rc v thres 63% 5 v = positive going threshold for 5v logic (b option) v l .3v = low level of the logic signal into the rc r del 100 = timing values c del 1nf = t del r del ? c del ln v l v thres ? v h v l ? 1 + ? ? ? ? ? ? = t del 34.788 ns = nominal delay time for this example q g, gate charge (nc) 12 10 8 6 4 2 0 024681012141618202224 v gs gate-source voltage (v) figure 16. mosfet gate charge vs gate voltage v ds = 64v v ds = 40v (eq. 2) p d 2q c freq v gs r gate r gate r ds on () + -------------------------------------------- - i dd freq () v dd ? + ? ? ? ? =
ISL89163, isl89164, isl89165 11 fn7707.0 october 12, 2010 typical application circuits this drive circuit provides primary to secondary line isolation. a controller, on the primary side, is the source of the sr control signals outlln and outlrn signals. the secondary side signals, v1 and v2 are rectified by the dual diode, d9, to genera te the secondary side bias for u4. v1 and v3 are also inverted by q100 and q101 and the rising edges are delayed by r27/c10 and r28/c9 respectively to generate the sr drive signals, lrn and lln. for more complete information on this sr drive circuit, and other applications for the ISL89163/4/5, refer to an1603 ?isl6752_54 evaluation board application note?. general pcb layout guidelines the ac performance of the ISL89163, isl89164, isl89165 depends significantly on the design of the pc board. the following layout design guidelines are recommended to achieve optimum performance: ? place the driver as close as possible to the driven power fet. ? understand where the switching power currents flow. the high amplitude di/dt currents of the driven power fet will induce significant voltage transients on the associated traces. ? keep power loops as short as possible by paralleling the source and return traces. ? use planes where practical; they are usually more effective than parallel traces. ? avoid paralleling high amplitude di/dt traces with low level signal lines. high di/dt will induce currents and consequently, noise voltages in the low level signal lines. ? when practical, minimize impedances in low level signal circuits. the noise, magnetically induced on a 10k resistor, is 10x larger than the noise on a 1k resistor. ? be aware of magnetic fields emanating from transformers and inductors. gaps in these structures are especially bad for emitting flux. ? if you must have traces close to magnetic devices, align the traces so that they are parallel to the flux lines to minimize coupling. ? the use of low inductance components such as chip resistors and chip capacitors is highly recommended. ? use decoupling capacitors to reduce the influence of parasitic inductance in the vdd and gnd leads. to be effective, these caps must also have the shortest possible conduction paths. if vias are used, connect several paralleled vias to reduce the inductance of the vias. ? it may be necessary to add resistance to dampen resonating parasitic circuits especially on outa and outb. if an external gate resistor is unacceptable, then the layout must be improved to minimize lead inductance. ? keep high dv/dt nodes away from low level circuits. guard banding can be used to shunt away dv/dt injected currents from sensitive circuits. this is especially true for control circuits that source the input signals to the ISL89163, isl89164, isl89165. ? avoid having a signal ground plane under a high amplitude dv/dt circuit. this will inject di/dt currents into the signal ground paths. ? do power dissipation and voltage drop calculations of the power traces. many pcb/cad programs have built in tools for calculation of trace resistance. ? large power components (power fets, electrolytic caps, power resistors, etc.) will have internal parasitic inductance which cannot be eliminated. this must be accounted for in the pcb layout and circuit design. ? if you simulate your circuits, consider including parasitic components especially parasitic inductance. r27 u4 u4 v1 v1 v2 enable r-sr lsr v4 v3 t6 outlln outlrn lln lrn lln pwm ISL89163 d9 c10 c9 r28 /outlrn v2 /outlln lrl v3 v4 lrn vbias q100 q101 el7212 red dashed lines point out the turn-on delay of the srs when pwm goes low c123 primary to secondary side self biasing, isolated sr drive
ISL89163, isl89164, isl89165 12 fn7707.0 october 12, 2010 general epad heatsinking considerations the thermal pad is electrically connected to the gnd supply through the ic substrate. the epad of the ISL89163, isl89164, isl89165 has two main functions: to provide a quiet gnd for the input threshold comparators and to provide heat sinking for the ic. the epad must be connected to a ground plane and no switching currents from the driven fet should pass through the ground plane under the ic. figure 17 is a pcb layout example of how to use vias to remove heat from the ic through the epad. for maximum heatsinking, it is recommended that a ground plane, connected to the epad, be added to both sides of the pcb. a via array, within the area of the epad, will conduct heat from the epad to the gnd plane on the bottom layer. the number of vias and the size of the gnd planes required for adequate heatsinking is determined by the power dissipated by the ISL89163, isl89164, isl89165, the air flow and the maximum temperature of the air around the ic. epad gnd plane component layer epad gnd plane bottom layer figure 17. typical pcb pattern for thermal vias
ISL89163, isl89164, isl89165 13 fn7707.0 october 12, 2010 products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: ISL89163, isl89164, isl89165 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/sear revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 10/12/10 fn7707.0 initial release
ISL89163, isl89164, isl89165 14 fn7707.0 october 12, 2010 package outline drawing l8.3x3i 8 lead thin dual flat no-lead plastic package rev 1 6/09 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recommended land pattern top view side view c 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 3.00 a b 3.00 (4x) 0.15 6 pin 1 index area pin #1 index area 6x 0.65 1.64 +0.10/ - 0.15 8 1 8x 0.400 0.10 6 max 0.80 see detail "x" 0.08 0.10 c c c ( 2.80 ) (1.64) ( 8 x 0.30) ( 8x 0.60) ( 2.38 ) ( 1.95) 2.38 0.10 8x 0.30 a mc b 4 2x 1.950 +0.10/ - 0.15 (6x 0.65) 4 5 pin 1
ISL89163, isl89164, isl89165 15 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7707.0 october 12, 2010 for additional products, see www.intersil.com/product_tree small outline exposed pad plastic packages (epsoic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m p1 123 p bottom view n top view side view m8.15d 8 lead narrow body small outline exposed pad plastic package symbol inches millimeters notes min max min max a 0.059 0.067 1.52 1.72 - a1 0.003 0.009 0.10 0.25 - b 0.0138 0.0192 0.36 0.46 9 c 0.0075 0.0098 0.19 0.25 - d 0.189 0.196 4.80 4.98 3 e 0.150 0.157 3.811 3.99 4 e 0.050 bsc 1.27 bsc - h 0.230 0.244 5.84 6.20 - h 0.010 0.019 0.25 0.50 5 l 0.016 0.050 0.41 1.27 6 n8 87 0 8 0 8 - p 0.118 0.137 3.00 3.50 11 p1 0.078 0.099 2.00 2.50 11 rev. 0 5/07 notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional . if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. 11. dimensions ?p? and ?p1? are t hermal and/or electrical enhanced variations. values shown are maximum size of exposed pad within lead count and body size.

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